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interger rf/if dual pll s1m8821/22/23 1 introduction the s1m8821/22/23 is a high performance dual frequency synthesizer with integrated prescalers designed for rf operation up to 1.2ghz/2.0ghz/2.5ghz and if operation up to 520mhz. the s1m8821/22/23 contains dual-modulus prescalers. the rf synthesizer adopts a 64/65 or a 128/129 prescaler(32/33 or 64/65 for the s1m8823) and the if synthesizer adopts an 8/9 or a 16/17 prescaler. using a proprietary digital phase-locked-loop technique, the s1m8821/22/23 has linear phase detector characteristic and can be used for very stable, low noise local oscillator signal. supply voltage can range from 2.7v to 4.0v. the s1m8821/22/23 is now available in a 20-tssop/24-qfn package. features high operating frequency dual synthesizer ? s1m8821 : 0.1 to 1.2ghz (rf)/ 45 to 520mhz (if) ? s1m8822 : 0.2 to 2.0ghz (rf)/ 45 to 520mhz (if) ? s1m8823 : 0.5 to 2.5ghz (rf)/ 45 to 520mhz (if) very low current consumption(8821:3.5ma, 22:4.5ma, 23:5.5ma) operating voltage range : 2.7 to 4.0v selectable power saving mode(icc=1ua typical @3v) dual modulus prescaler : s1m8821/22 (rf) 64/65 or 128/129 s1m8823 (rf) 32/33 or 64/65 s1m8821/22/23 (if) 8/9 or 16/17 programmability via serial bus interface no dead-zone pfd variable charge pump output current high speed lock mode applications cellular telephone systems : s1m8821 portable wireless communications : s1m8822 (pcs/pcn, cordless) wireless local area networks (w-lans) : s1m8823 other wireless communication systems 20-tssop-bd44 24-qfn-3.5 4.5
s1m8821/22/23 interger rf/if dual pll 2 ordering information device package operating temperature S1M8821X01-R0T0 s1m8822x01-r0t0 s1m8823x01-r0t0 20-tssop-bd44 -40 to +85 c S1M8821X01-R0T0 s1m8822x01-r0t0 s1m8823x01-r0t0 24-qfn-3.5 4.5 -40 to +85 c
interger rf/if dual pll s1m8821/22/23 3 block diagram note: the pin numbers above are for 20-tssop package. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 fold data out multiplexer rf ld rf phase detector rf charge pump if ld if phase detector if charge pump +? rf prescaler prescaler control rf programmable counter rf n-latch rf r-latch rf reference counter if reference counter 20-bit shift register if r-latch if n-latch 2-bit control ?+ if prescaler prescaler control if counter programmable v dd 1 v p 1 cporf gnd f in rf f in rf gnd oscin gnd fold v dd 2 v p 2 cpoif gnd f in if f in if gnd le data clock
s1m8821/22/23 interger rf/if dual pll 4 pin configuration notes: 1. pin #9 = pin #17(internally connected). 2. do not tie up vp and vdd : vp is the source of digital noises. the power for analog part is supplied by vdd. if vp and vdd are tied together, noisy vp corrupts the power source for the analog part. v dd 1 vp1 cporf gnd finrf finrf gnd oscin gnd fold v dd 2 vp2 cpoif gnd finif finif gnd le data clock 1 20 2 3 4 5 6 7 8 20-lead(0.173 wide) thin shrink small 9 10 19 18 17 16 15 14 13 12 11 outline package(20-tssop) s1m8821 s1m8822 s1m8823 20-tssop (digital) (analog) (digital) (digital) (analog)
interger rf/if dual pll s1m8821/22/23 5 pin configuration(24-qfn, not to scale) notes: 1 pin #10 = pin #19(internally connected). 2. do not tie up vp and v dd : vp is the source of digital noises. the power for analog part is supplied by v dd. if vp and v dd are tied together, noisy vp corrupts the power source for the analog part. v dd 1 vp1 cporf gnd finrf finrf gnd oscin gnd fold v dd 2 vp2 cpoif gnd finif finif gnd le data clock 1 8 24 7 6 5 4 3 2 23 9 22 21 20 19 18 17 16 15 14 13 12 10 11 n/c n/c n/c n/c s1m8822 s1m8823 s1m8821 (24-qfn) package 24-qfn 24 pin quad flat non-leaded (digital) (digital) (digital) (analog) (analog) * n/c pins must be connected to gnd(to analog gnd if possible).
s1m8821/22/23 interger rf/if dual pll 6 pin description pin no (20tssop) pin no (24qfn) symbol i / o description 124v dd 1 - power supply voltage input for the rf pll part. v dd 1 must equal v dd 2. in order to reject supply noise, bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane. - 1 - n/c no connection. 2 2 vp1 - power supply voltage input for rf charge pump( v dd 1). 3 3 cporf o internal rf charge pump output for connection to an external loop filter whose filtered output drives an external vco. 4 4 gnd - ground for rf digital blocks. 5 5 finrf i rf prescaler input. the signal comes from the external vco. 66finrf i the complementary input of the rf prescaler. a bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. the bypass capacitor is optional with some loss of sensitivity. 7 7 gnd - ground for rf analog blocks. 8 8 oscin i reference counter input. tcxo is connected via a coupling capacitor. - 9 - n/c no connection. 9 10 gnd - ground for if digital blocks. 10 11 f old o multiplexed output of the rf/if programmable counters, the reference counters, the lock detect signals and the shift registers. the output level is cmos level. (see f out programmable truth table) 11 12 clock i cmos clock input. serial data for the various counters is transferred into the 22-bit shift register on the rising edge of the clock signal. - 13 - n/c no connection. 12 14 data i binary serial data input. the msb of cmos input data is entered first. the control bits are on the last two bits. cmos input. 13 15 le i load enable cmos input. when le becomes high, the data in the shift register is loaded into one of the four latches (by the control bits). 14 16 gnd - ground for if analog blocks.
interger rf/if dual pll s1m8821/22/23 7 pin description (continued) pin no (20tssop) pin no (24qfn) symbol i / o description 15 17 finif i the complementary input of the if prescaler. a bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. the bypass capacitor is optional with some loss of sensitivity. 16 18 finif i if prescaler input. the signal comes from the external vco. 17 19 gnd - ground for if digital blocks. 18 20 cpoif o internal if charge pump output for connection to an external loop filter whose filtered output drives an external vco. - 21 - n/c no connection. 19 22 vp2 - power supply voltage input for if charge pump( v dd 2) 20 23 v dd 2 - power supply voltage input for the if pll part. v dd 1 must equal v dd 2. in order to reject supply noise, bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane.
s1m8821/22/23 interger rf/if dual pll 8 equivalent circuit diagram clock, data, le fold oscin cporf, cpoif finrf, finrf , finif, finif finrf, finif finrf , finif v bias
interger rf/if dual pll s1m8821/22/23 9 absolute maximum ratings electrostatic characteristics these devices are esd sensitive. these devices must be handled in the esd protected environment. characteristic symbol value unit power supply voltage v dd 0 to 4.0 v power dissipation p d 600 mw operating temperature ta -40 to +85 o c c storage temperature t stg -65 to +150 o c c characteristic pin no. esd level unit human body model all < 2000 v machine model all < 300 v charged device model all < 800 v
s1m8821/22/23 interger rf/if dual pll 10 electrical characteristics (v dd =3.0v, v p =3.0v, ta = = = = 25 c, unless otherwise specified) characteristic symbol test conditions min. typ. max. unit power supply voltage v dd 2.7 3.0 4.0 v v p v dd 3.0 4.0 power supply current s1m8823 rf + if i dd v dd =2.7v to 4.0v 5.5 ma s1m8823 rf only 4.0 s1m8822 rf + if 4.5 s1m8822 rf only 3.0 s1m8821 rf + if 3.5 s1m8821 rf only 2.0 s1m882x if only 1.5 power down current i pwdn v dd =3.0v 1.0 10 a digital inputs : clock, data and le high-level input voltage v ih v dd =2.7v to 4.0v 0.7v dd v low-level input voltage v il v dd =2.7v to 4.0v 0.3v dd v high-level input current i ih v ih = v dd =4.0v -1.0 +1.0 a low-level input current i il v il =0v, v dd =4.0v -1.0 +1.0 a reference oscillator input : oscin input current i ihr v ih = v dd =4.0v +100 a i ilr v il =0v, v dd =4.0v -100 a digital output : fold high level output voltage v oh iout = -500 av dd -0.4 v low level output voltage v ol iout = +500 a0.4v
interger rf/if dual pll s1m8821/22/23 11 electrical characteristics (continued) (v dd =3.0v, v p =3.0v, ta = = = = 25 c, unless otherwise specified) characteristic symbol test conditions min. typ. max. unit charge pump outputs : cporf, cpoif charge pump output current i cp-src v cp =v p /2, i cpo =low -1.0 ma i cp-sink v cp =v p /2, i cpo =low +1.0 i cp-src v cp =v p /2, i cpo =high -4.0 i cp-sink v cp =v p /2, i cpo =high +4.0 charge pump leakage current i cpl 0.5v v cp v p -0.5v -2.5 +2.5 na output current sink vs. source mismatch* i cp-sink vs i cp-src v cp =v p /2 3 10 % output current magnitude variation vs. temperature** i cp vs t v cp =v p /2 10 % output current magnitude variation vs. voltage*** i cp vs v cp 0.5v v cp v p -0.5v 10 15 % programmable divider operating frequency s1m8823 finrf v dd =2.7v to 4.0v 0.5 2.5 ghz s1m8822 0.2 2.0 s1m8821 0.1 1.2 operating frequency finif v dd =3.0v 45 520 mhz rf input sensitivity p fin rf v dd =3.0v -15 0 dbm v dd =4.0v -10 0 if input sensitivity p fin if v dd =2.7v to 4.0v -10 0 dbm phase detector frequency f pd 10 mhz reference divider operating frequency oscin 5 40 mhz input sensitivity v oscin 0.5 v pp
s1m8821/22/23 interger rf/if dual pll 12 electrical characteristics (continued) (v dd =3.0v, v p =3.0v, ta = = = = 25 c, unless otherwise specified ) ia=charge pump sink current at vcp=vp- ? v, ib=charge pump sink current at vcp=vp/2, ic=charge pump sink current at vcp= ? v id=charge pump source current at vcp=vp- ? v, ie=charge pump source current at vcp=vp/2, if=charge pump source current at vcp= ? v ? v=voltage offset from positive(for sink current) and negative(for source current) points from which the charge pump currents become flat. * output current sink vs. source mismatch = [| ib|-|ie|] / [0.5 * {| ib|+|ie|}] * 100 (%) ** output current magnitude variation vs. temperature = [| ib @any temp.| - |ib @ 25 c|] / | ib @ 25 c| * 100 (%) and [|ie @any temp.| - |ie @ 25 c|] / |ie @ 25 c| * 100 (%) *** output current magnitude variation vs. voltage = [0.5 * {|ia|-|ic|}] / [0.5 * {|ia|+|ic|}] * 100 (%) and [0.5 * {|id|-|if|}] / [0.5 * {|id|+|if|}] * 100 (%) characteristic symbol test conditions min. typ. max. unit serial data control clock frequency f clock 10 mhz clock pulse width high t cwh 50 ns clock pulse width low t cwl 50 ns data set up time to clock risng edge t ds 50 ns data hold time after clock rising edge t dh 10 ns le pulse width t lew 50 ns clock rising edge to le rising edge t cle 50 ns
interger rf/if dual pll s1m8821/22/23 13 functional description the samsung s1m8821/22/23 are dual pll frequency synthesizer ics. s1m8821/22/23 combined with external lpfs and external vcos form pll frequency synthesizers. they include serial data control, r counter, n counter, prescaler, phase detector, charge pump, and etc. serial data is moved into 20-bit shift register on the rising edge of the clock. these data enters msb first. when le becomes high, data in the shift register is moved into one of the 4 latches(by the 2-bit control). the divide ratios of the prescaler and the counters are determined by the data stored in the latches. the external vco output signal is divided by the prescaler and the n counter. external reference signal is divided by the r counter. these two signals are the two input signals to the phase detector. the phase detector drives the charge pump by comparing frequencies and phases of the above two signals. the charge pump and the external lpf make the control voltage for the external vco and finally the vco generates the appropriate frequency signal. serial data input timing msb lsb n20(r20) n19(r19) n10(r10) n9(r9) c2 c1 t ds t cwl t cwh t lew t dh data clock le t cle
s1m8821/22/23 interger rf/if dual pll 14 programming description control bits programmable reference counter(if / rf r counter) if the control bits are 00(if) or 01(rf), data is moved from the 20-bit shift register into the r-latch which sets the reference counter. serial data format is shown in the table below. 15-bit programmable reference counter ratio division ratio : 3 to 32767 data are shifted in msb first control bits data location c1 c2 0 0 if r counter 0 1 rf r counter 1 0 if n counter 1 1 rf n counter division ratio r 15 r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 3 000000000000011 4 000000000000100 2 222222222222222 32767111111111111111 c1 c2 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 r 15 r 16 r 17 r 18 r 19 r 20 lsb msb program modes division ratio of the r counter, r control bits
interger rf/if dual pll s1m8821/22/23 15 programmable counter(n counter) if the control bits are 10(if) or 11(rf), data is transferred from the 20-bit shift register into the n-latch. n counter consists of 7-bit swallow counter(a counter) and 11-bit main counter(b counter). serial data format is shown below. 7-bit swallow counter division ratio(a counter) 11-bit main counter division ratio(b counter) division ratio : 3 to 2047 rf if division ratio(a) n 7 n 6 n 5 n 4 n 3 n 2 n 1 division ratio(a) n 7 n 6 n 5 n 4 n 3 n 2 n 1 0 0000000 0 xxx0000 1 0000001 1 xxx0001 ? ??????? ? ??????? 127 1111111 15 xxx1111 division ratio : 0 to 127 b > a division ratio : 0 to 15 b > a x = don?t care condition division ratio n 18 n 17 n 16 n 15 n 14 n 13 n 12 n 11 n 10 n 9 n 8 3 00000000011 4 00000000100 ? ??????????? 2047 11111111111 c1 c2 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11 n 12 n 13 n 14 n 15 n 16 n 17 n 18 n 19 n 20 lsb msb program modes division ratio of the n counter, n control bits
s1m8821/22/23 interger rf/if dual pll 16 pulse swallow function f vco =[ ( p x b ) + a ] x f oscin / r f vco : external vco output frequency p : preset modulus of dual modulus prescaler (for s1m8821/22 rf:p=64 or 128, for s1m8823 rf:p=32 or 64, for if: p=8 or 16) b : 11-bit main counter division ratio (3 b 2047) a : 7-bit swallow counter division ratio (for rf: 0 a 127, for if: 0 a 15, a b) f oscin : external reference frequency(from external oscillator) r : 15-bit reference counter division ratio (3 r 32767) program mode mode select truth table * the charge pump output current of i cpo low = 1/4 i cpo high. c1 c2 r16 r17 r18 r19 r20 0 0 if phase detector polarity if i cpo if cpoif high impedance if ld if fo 01 rf phase detector polarity rf i cpo rf cpoif high impedance rf ld rf fo c1 c2 n19 n20 1 0 if prescaler pwdn if 1 1 rf prescaler pwdn rf phase detector polarity cpoif high impedance i cpo if prescaler rf prescaler s1m8821/22 (s1m8823) pwdn 0 negative normal operation low 8/9 64/65 (32/33) pwr up 1 positive high impedance high 16/17 128/129 (64/65) pwr dn
interger rf/if dual pll s1m8821/22/23 17 phase detector polarity depending on vco characteristics, r16 bit should be set as follows : vco characteristics are positive like (1) : r16 high vco characteristics are negative like (2) : r16 low fold (pin10) output truth table ? when the pll is locked and a lock detect mode is selected, the fold output is high, with narrow pulses low. ? counter reset mode resets r & n counters. ? the high speed lock mode sets the fold output pin to be connected to ground with a low impedance ( 110 ? ). rf r19 (rf ld) if r19 (if ld) rf r20 (rf fo) if r20 (if fo) fold output state 0000 disabled (default low) 0100 if lock detect 1000 rf lock detect 1100 rf and if lock detect 0001 if reference divider output 0010 rf reference divider output 0101 if programmable divider output 0110 rf programmable divider output 0011 high speed lock mode 0111 if counter reset 1011 rf counter reset 1111 rf and if counter reset (1) (2) vco input voltage vco output frequency vco characteristics
s1m8821/22/23 interger rf/if dual pll 18 functional description (continued) powerdown mode operation there are synchronous and asynchronous powerdown modes for s1m8821/22/23. synchronous powerdown mode occurs if r18 bit is low, n20 bit is high and charge pump output is in high impedance state. in the synchronous power down mode, the powerdown function is activated by the charge pump to diminish unwanted frequency jumps. asynchronous powerdown mode occurs if r18 bit is high and n20 bit is high. when the pll goes to either synchronous or asynchronous powerdown mode, preamp becomes debiased, r & n counters keeps their load conditions and the charge pump becomes high impedance state. the oscillator circuitry function becomes disabled only when both if and rf powerdown bits are activated, i.e. n20 high. the pll returns to an active powerup mode when n20 bit becomes low(either in synchronous or asynchronous modes). phase detector and charge pump characteristics phase difference detection range : -2 to +2 when r16 = high r18 n20 powerdown mode status 0 0 pll active 1 0 pll active, only charge pump high impedance 0 1 synchronous powerdown 1 1 asynchronous powerdown fr fp ld fr>fp fr=fp fr interger rf/if dual pll s1m8821/22/23 19 rf sensitivity measurement circuit rf signal generator frequency counter pc parallel port 50 ? microstrip 100pf 51 ? 100pf 12k ? 39k ? f in f in osc in fold 2.7v to 4.0v v dd v p le data clock 100pf 100pf 2.2 f 2.2 f ** n=10,000 r=50 p=64 ** sensitivity limit is determined when the error of the divided rf output( fold) becomes 1 hz. 10db attn
s1m8821/22/23 interger rf/if dual pll 20 typical application circuit ** the role of rin : rin makes vco output power go to the load rather than the pll. the value of rin depends on the vco power level. 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 fold gnd oscin gnd finrf f in rf gnd cporf v p 1v dd 1 clock data le gnd f in if f in if gnd cpoif v p 2v dd 2 vco vco from controller if out 100pf 100pf 10pf r in r2 c3 c4 100pf vp 0.01 f 18 ? v dd 100pf 0.01 f 0.01 f 0.01 f 100pf 0.01 f v dd v p 100pf 0.01 f r1 c1 c2 10pf 100pf 100pf rf out 1000pf fold reference input 51 ? r in 18 ? s1m8821/22/23 . cdma : ucva4x103a . k-pcs : ucvw4x102a . us-pcs : ucva3x120a
interger rf/if dual pll s1m8821/22/23 21 package dimensions #20 #11 #1 #10 6.40 0.30 0.252 0.012 6.40 ?? 0.20 0.252 ?? 0.008 6.90 0.272 max 0.90 0.20 0.059 0.008 1.10 0.073 max 0.30 0.012 0.22 ?? 0.10 0.009 ?? 0.004 0.65 0.026 0.05 0.002 min 0.10max 0.004max 4.40 ?? 0.20 0.173 ?? 0.008 5.72 0.225 0.50 ?? 0.20 0.020 ?? 0.008 0.15 x -0.05 0.006 x -0.002 +0.10 +0.004 0 ~ 8 o 20-lead tssop package (samsung 20-tssop-bd44)
s1m8821/22/23 interger rf/if dual pll 22 package dimensions (24-qfn) 0.27 + 0.05 0.70 + 0.05 1.00max 3.50 + 0.10 4.50 + 0.10 b a #1 index area c 0.08 c (0.05) 0.10 2x4.00 0.10 c 2x (0.05) #24 4x0.50 + 0.10 #1 #1 id mark 0.10 c 2x 20x0.50 2x1.00 24x0.30 + 0.05 m c b c s

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